#include /*** Device configuration registers ***/ /* * CPU System Clock Postscaler = [OSC1/OSC2 Src: /1][96MHz PLL Src: /2] * Fail-Safe Clock Monitor Enable = Disabled * Internal External Switch Over Mode = Disabled * Oscillator = HS: HS+PLL, USB-HS * 96MHz PLL Prescaler = Divide by 5 (20MHz input) * Full-Speed USB Clock Source Selection = Clock src from 96MHz PLL/2 */ __CONFIG(1, 0xFFE7 & FCMDIS & IESODIS & 0xFFFF & PLLDIV5 & USBPLL); /* * Brown Out Detect = Disabled in hardware, SBOREN disabled * Brown Out Voltage = 4.5V * Power Up Timer = Enabled * USB Voltage Regulator = Disabled * Watchdog Timer = Disabled-Controlled by SWDTEN bit * Watchdog Postscaler = 1:1 */ __CONFIG(2, BORDIS & BORV45 & PWRTEN & 0xFFDF & WDTDIS & WDTPS1); /* * CCP2 Mux = RB3 * Low Power Timer1 Osc Enable = Disabled * Master Clear Enable = MCLR Enabled,RE3 Disabled * PortB A/D Enable = PORTB[4:0] configured as digital I/O on RESET */ __CONFIG(3, CCP2RB3 & LPT1DIS & MCLREN & 0xFDFF); /* * Background Debug = Disabled * Extended CPU Enable = Disabled * Low Voltage Program = Disabled * Stack Overflow Reset = Disabled */ __CONFIG(4, DEBUGDIS & XINSTDIS & LVPDIS & STVRDIS); /* * Code Protect Boot = Disabled * Data EE Read Protect = Disabled * Code Protect 00800-01FFF = Disabled * Code Protect 02000-03FFF = Disabled * Code Protect 04000-05FFF = Disabled * Code Protect 06000-07FFF = Disabled */ __CONFIG(5, 0xFFFF); /* * Table Write Protect Boot = Disabled * Config. Write Protect = Disabled * Data EE Write Protect = Disabled * Table Write Protect 00800-01FFF = Disabled * Table Write Protect 02000-03FFF = Disabled * Table Write Protect 04000-05FFF = Disabled * Table Write Protect 06000-07FFF = Disabled */ __CONFIG(6, 0xFFFF); /* * Table Read Protect Boot = Disabled * Table Read Protect 00800-01FFF = Disabled * Table Read Protect 02000-03FFF = Disabled * Table Read Protect 04000-05FFF = Disabled * Table Read Protect 06000-07FFF = Disabled */ __CONFIG(7, 0xFFFF); // Peripheral initialization function void init(void){ /***** Common Code **** * Peripheral interrupts will be disabled * Interrupts are globally disabled */ INTCON = 0b00000000; /***** 18F2550 Code **** * Interrupt priority system not required */ RCON = 0b00000000; }